DPDK logo

Elixir Cross Referencer

   1
   2
   3
   4
   5
   6
   7
   8
   9
  10
  11
  12
  13
  14
  15
  16
  17
  18
  19
  20
  21
  22
  23
  24
  25
  26
  27
  28
  29
  30
  31
  32
  33
  34
  35
  36
  37
  38
  39
  40
  41
  42
  43
  44
  45
  46
  47
  48
  49
  50
  51
  52
  53
  54
  55
  56
  57
  58
  59
  60
  61
  62
  63
  64
  65
  66
  67
  68
  69
  70
  71
  72
  73
  74
  75
  76
  77
  78
  79
  80
  81
  82
  83
  84
  85
  86
  87
  88
  89
  90
  91
  92
  93
  94
  95
  96
  97
  98
  99
 100
 101
 102
 103
 104
 105
 106
 107
 108
 109
 110
 111
 112
 113
 114
 115
 116
 117
 118
 119
 120
 121
 122
 123
 124
 125
 126
 127
 128
 129
 130
 131
 132
 133
 134
 135
 136
 137
 138
 139
 140
 141
 142
 143
 144
 145
 146
 147
 148
 149
 150
 151
 152
 153
 154
 155
 156
 157
 158
 159
 160
 161
 162
 163
 164
 165
 166
 167
 168
 169
 170
 171
 172
 173
 174
 175
 176
 177
 178
 179
 180
 181
 182
 183
 184
 185
 186
 187
 188
 189
 190
 191
 192
 193
 194
 195
 196
 197
 198
 199
 200
 201
 202
 203
 204
 205
 206
 207
 208
 209
 210
 211
 212
 213
 214
 215
 216
 217
 218
 219
 220
 221
 222
 223
 224
 225
 226
 227
 228
 229
 230
 231
 232
 233
 234
 235
 236
 237
 238
 239
 240
 241
 242
 243
 244
 245
 246
 247
 248
 249
 250
 251
 252
 253
 254
 255
 256
 257
 258
 259
 260
 261
 262
 263
 264
 265
 266
 267
 268
 269
 270
 271
 272
 273
 274
 275
 276
 277
 278
 279
 280
 281
 282
 283
 284
 285
 286
 287
 288
 289
 290
 291
 292
 293
 294
 295
 296
 297
 298
 299
 300
 301
 302
 303
 304
 305
 306
 307
 308
 309
 310
 311
 312
 313
 314
 315
 316
 317
 318
 319
 320
 321
 322
 323
 324
 325
 326
 327
 328
 329
 330
 331
 332
 333
 334
 335
 336
 337
 338
 339
 340
 341
 342
 343
 344
 345
 346
 347
 348
 349
 350
 351
 352
 353
 354
 355
 356
 357
 358
 359
 360
 361
 362
 363
 364
 365
 366
 367
 368
 369
 370
 371
 372
 373
 374
 375
 376
 377
 378
 379
 380
 381
 382
 383
 384
 385
 386
 387
 388
 389
 390
 391
 392
 393
 394
 395
 396
 397
 398
 399
 400
 401
 402
 403
 404
 405
 406
 407
 408
 409
 410
 411
 412
 413
 414
 415
 416
 417
 418
 419
 420
 421
 422
 423
 424
 425
 426
 427
 428
 429
 430
 431
 432
 433
 434
 435
 436
 437
 438
 439
 440
 441
 442
 443
 444
 445
 446
 447
 448
 449
 450
 451
 452
 453
 454
 455
 456
 457
 458
 459
 460
 461
 462
 463
 464
 465
 466
 467
 468
 469
 470
 471
 472
 473
 474
 475
 476
 477
 478
 479
 480
 481
 482
 483
 484
 485
 486
 487
 488
 489
 490
 491
 492
 493
 494
 495
 496
 497
 498
 499
 500
 501
 502
 503
 504
 505
 506
 507
 508
 509
 510
 511
 512
 513
 514
 515
 516
 517
 518
 519
 520
 521
 522
 523
 524
 525
 526
 527
 528
 529
 530
 531
 532
 533
 534
 535
 536
 537
 538
 539
 540
 541
 542
 543
 544
 545
 546
 547
 548
 549
 550
 551
 552
 553
 554
 555
 556
 557
 558
 559
 560
 561
 562
 563
 564
 565
 566
 567
 568
 569
 570
 571
 572
 573
 574
 575
 576
 577
 578
 579
 580
 581
 582
 583
 584
 585
 586
 587
 588
 589
 590
 591
 592
 593
 594
 595
 596
 597
 598
 599
 600
 601
 602
 603
 604
 605
 606
 607
 608
 609
 610
 611
 612
 613
 614
 615
 616
 617
 618
 619
 620
 621
 622
 623
 624
 625
 626
 627
 628
 629
 630
 631
 632
 633
 634
 635
 636
 637
 638
 639
 640
 641
 642
 643
 644
 645
 646
 647
 648
 649
 650
 651
 652
 653
 654
 655
 656
 657
 658
 659
 660
 661
 662
 663
 664
 665
 666
 667
 668
 669
 670
 671
 672
 673
 674
 675
 676
 677
 678
 679
 680
 681
 682
 683
 684
 685
 686
 687
 688
 689
 690
 691
 692
 693
 694
 695
 696
 697
 698
 699
 700
 701
 702
 703
 704
 705
 706
 707
 708
 709
 710
 711
 712
 713
 714
 715
 716
 717
 718
 719
 720
 721
 722
 723
 724
 725
 726
 727
 728
 729
 730
 731
 732
 733
 734
 735
 736
 737
 738
 739
 740
 741
 742
 743
 744
 745
 746
 747
 748
 749
 750
 751
 752
 753
 754
 755
 756
 757
 758
 759
 760
 761
 762
 763
 764
 765
 766
 767
 768
 769
 770
 771
 772
 773
 774
 775
 776
 777
 778
 779
 780
 781
 782
 783
 784
 785
 786
 787
 788
 789
 790
 791
 792
 793
 794
 795
 796
 797
 798
 799
 800
 801
 802
 803
 804
 805
 806
 807
 808
 809
 810
 811
 812
 813
 814
 815
 816
 817
 818
 819
 820
 821
 822
 823
 824
 825
 826
 827
 828
 829
 830
 831
 832
 833
 834
 835
 836
 837
 838
 839
 840
 841
 842
 843
 844
 845
 846
 847
 848
 849
 850
 851
 852
 853
 854
 855
 856
 857
 858
 859
 860
 861
 862
 863
 864
 865
 866
 867
 868
 869
 870
 871
 872
 873
 874
 875
 876
 877
 878
 879
 880
 881
 882
 883
 884
 885
 886
 887
 888
 889
 890
 891
 892
 893
 894
 895
 896
 897
 898
 899
 900
 901
 902
 903
 904
 905
 906
 907
 908
 909
 910
 911
 912
 913
 914
 915
 916
 917
 918
 919
 920
 921
 922
 923
 924
 925
 926
 927
 928
 929
 930
 931
 932
 933
 934
 935
 936
 937
 938
 939
 940
 941
 942
 943
 944
 945
 946
 947
 948
 949
 950
 951
 952
 953
 954
 955
 956
 957
 958
 959
 960
 961
 962
 963
 964
 965
 966
 967
 968
 969
 970
 971
 972
 973
 974
 975
 976
 977
 978
 979
 980
 981
 982
 983
 984
 985
 986
 987
 988
 989
 990
 991
 992
 993
 994
 995
 996
 997
 998
 999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2016-2020 Intel Corporation
 */

#include <inttypes.h>

#include <rte_malloc.h>
#include <rte_eventdev.h>

#include "dlb2_priv.h"
#include "dlb2_inline_fns.h"
#include "pf/base/dlb2_regs.h"

enum dlb2_xstats_type {
	/* common to device and port */
	rx_ok,				/**< Receive an event */
	rx_drop,                        /**< Error bit set in received QE */
	rx_interrupt_wait,		/**< Wait on an interrupt */
	rx_umonitor_umwait,		/**< Block using umwait */
	tx_ok,				/**< Transmit an event */
	total_polls,			/**< Call dequeue_burst */
	zero_polls,			/**< Call dequeue burst and return 0 */
	tx_nospc_ldb_hw_credits,	/**< Insufficient LDB h/w credits */
	tx_nospc_dir_hw_credits,	/**< Insufficient DIR h/w credits */
	tx_nospc_hw_credits,		/**< Insufficient h/w credits */
	tx_nospc_inflight_max,		/**< Reach the new_event_threshold */
	tx_nospc_new_event_limit,	/**< Insufficient s/w credits */
	tx_nospc_inflight_credits,	/**< Port has too few s/w credits */
	/* device specific */
	nb_events_limit,
	inflight_events,
	ldb_pool_size,
	dir_pool_size,
	pool_size,
	/* port specific */
	tx_new,				/**< Send an OP_NEW event */
	tx_fwd,				/**< Send an OP_FORWARD event */
	tx_rel,				/**< Send an OP_RELEASE event */
	tx_implicit_rel,		/**< Issue an implicit event release */
	tx_sched_ordered,		/**< Send a SCHED_TYPE_ORDERED event */
	tx_sched_unordered,		/**< Send a SCHED_TYPE_PARALLEL event */
	tx_sched_atomic,		/**< Send a SCHED_TYPE_ATOMIC event */
	tx_sched_directed,		/**< Send a directed event */
	tx_invalid,                     /**< Send an event with an invalid op */
	outstanding_releases,		/**< # of releases a port owes */
	max_outstanding_releases,	/**< max # of releases a port can owe */
	rx_sched_ordered,		/**< Dequeue an ordered event */
	rx_sched_unordered,		/**< Dequeue an unordered event */
	rx_sched_atomic,		/**< Dequeue an atomic event */
	rx_sched_directed,		/**< Dequeue an directed event */
	rx_sched_invalid,               /**< Dequeue event sched type invalid */
	/* common to port and queue */
	is_configured,			/**< Port is configured */
	is_load_balanced,		/**< Port is LDB */
	hw_id,				/**< Hardware ID */
	/* queue specific */
	num_links,			/**< Number of ports linked */
	sched_type,			/**< Queue sched type */
	enq_ok,				/**< # events enqueued to the queue */
	current_depth,			/**< Current queue depth */
	depth_threshold,		/**< Programmed depth threshold */
	depth_le50_threshold,
	/**< Depth LE to 50% of the configured hardware threshold */
	depth_gt50_le75_threshold,
	/**< Depth GT 50%, but LE to 75% of the configured hardware threshold */
	depth_gt75_le100_threshold,
	/**< Depth GT 75%. but LE to the configured hardware threshold */
	depth_gt100_threshold
	/**< Depth GT 100% of the configured hw threshold */
};

typedef uint64_t (*dlb2_xstats_fn)(struct dlb2_eventdev *dlb2,
		uint16_t obj_idx, /* port or queue id */
		enum dlb2_xstats_type stat, int extra_arg);

enum dlb2_xstats_fn_type {
	DLB2_XSTATS_FN_DEV,
	DLB2_XSTATS_FN_PORT,
	DLB2_XSTATS_FN_QUEUE
};

struct dlb2_xstats_entry {
	struct rte_event_dev_xstats_name name;
	uint64_t reset_value; /* an offset to be taken away to emulate resets */
	enum dlb2_xstats_fn_type fn_id;
	enum dlb2_xstats_type stat;
	enum rte_event_dev_xstats_mode mode;
	int extra_arg;
	uint16_t obj_idx;
	uint8_t reset_allowed; /* when set, this value can be reset */
};

/* Some device stats are simply a summation of the corresponding port values */
static uint64_t
dlb2_device_traffic_stat_get(struct dlb2_eventdev *dlb2,
			     int which_stat)
{
	int i;
	uint64_t val = 0;

	for (i = 0; i < DLB2_MAX_NUM_PORTS(dlb2->version); i++) {
		struct dlb2_eventdev_port *port = &dlb2->ev_ports[i];

		if (!port->setup_done)
			continue;

		switch (which_stat) {
		case rx_ok:
			val += port->stats.traffic.rx_ok;
			break;
		case rx_drop:
			val += port->stats.traffic.rx_drop;
			break;
		case rx_interrupt_wait:
			val += port->stats.traffic.rx_interrupt_wait;
			break;
		case rx_umonitor_umwait:
			val += port->stats.traffic.rx_umonitor_umwait;
			break;
		case tx_ok:
			val += port->stats.traffic.tx_ok;
			break;
		case total_polls:
			val += port->stats.traffic.total_polls;
			break;
		case zero_polls:
			val += port->stats.traffic.zero_polls;
			break;
		case tx_nospc_ldb_hw_credits:
			val += port->stats.traffic.tx_nospc_ldb_hw_credits;
			break;
		case tx_nospc_dir_hw_credits:
			val += port->stats.traffic.tx_nospc_dir_hw_credits;
			break;
		case tx_nospc_hw_credits:
			val += port->stats.traffic.tx_nospc_hw_credits;
			break;
		case tx_nospc_inflight_max:
			val += port->stats.traffic.tx_nospc_inflight_max;
			break;
		case tx_nospc_new_event_limit:
			val += port->stats.traffic.tx_nospc_new_event_limit;
			break;
		case tx_nospc_inflight_credits:
			val += port->stats.traffic.tx_nospc_inflight_credits;
			break;
		default:
			return -1;
		}
	}
	return val;
}

static uint64_t
get_dev_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx __rte_unused,
	     enum dlb2_xstats_type type, int extra_arg __rte_unused)
{
	switch (type) {
	case rx_ok:
	case rx_drop:
	case rx_interrupt_wait:
	case rx_umonitor_umwait:
	case tx_ok:
	case total_polls:
	case zero_polls:
	case tx_nospc_ldb_hw_credits:
	case tx_nospc_dir_hw_credits:
	case tx_nospc_hw_credits:
	case tx_nospc_inflight_max:
	case tx_nospc_new_event_limit:
	case tx_nospc_inflight_credits:
		return dlb2_device_traffic_stat_get(dlb2, type);
	case nb_events_limit:
		return dlb2->new_event_limit;
	case inflight_events:
		return __atomic_load_n(&dlb2->inflights, __ATOMIC_SEQ_CST);
	case ldb_pool_size:
		return dlb2->num_ldb_credits;
	case dir_pool_size:
		return dlb2->num_dir_credits;
	case pool_size:
		return dlb2->num_credits;
	default: return -1;
	}
}

static uint64_t
get_port_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx,
	      enum dlb2_xstats_type type, int extra_arg __rte_unused)
{
	struct dlb2_eventdev_port *ev_port = &dlb2->ev_ports[obj_idx];

	switch (type) {
	case rx_ok: return ev_port->stats.traffic.rx_ok;

	case rx_drop: return ev_port->stats.traffic.rx_drop;

	case rx_interrupt_wait: return ev_port->stats.traffic.rx_interrupt_wait;

	case rx_umonitor_umwait:
		return ev_port->stats.traffic.rx_umonitor_umwait;

	case tx_ok: return ev_port->stats.traffic.tx_ok;

	case total_polls: return ev_port->stats.traffic.total_polls;

	case zero_polls: return ev_port->stats.traffic.zero_polls;

	case tx_nospc_ldb_hw_credits:
		return ev_port->stats.traffic.tx_nospc_ldb_hw_credits;

	case tx_nospc_dir_hw_credits:
		return ev_port->stats.traffic.tx_nospc_dir_hw_credits;

	case tx_nospc_hw_credits:
		return ev_port->stats.traffic.tx_nospc_hw_credits;

	case tx_nospc_inflight_max:
		return ev_port->stats.traffic.tx_nospc_inflight_max;

	case tx_nospc_new_event_limit:
		return ev_port->stats.traffic.tx_nospc_new_event_limit;

	case tx_nospc_inflight_credits:
		return ev_port->stats.traffic.tx_nospc_inflight_credits;

	case is_configured: return ev_port->setup_done;

	case is_load_balanced: return !ev_port->qm_port.is_directed;

	case hw_id: return ev_port->qm_port.id;

	case tx_new: return ev_port->stats.tx_op_cnt[RTE_EVENT_OP_NEW];

	case tx_fwd: return ev_port->stats.tx_op_cnt[RTE_EVENT_OP_FORWARD];

	case tx_rel: return ev_port->stats.tx_op_cnt[RTE_EVENT_OP_RELEASE];

	case tx_implicit_rel: return ev_port->stats.tx_implicit_rel;

	case tx_sched_ordered:
		return ev_port->stats.tx_sched_cnt[DLB2_SCHED_ORDERED];

	case tx_sched_unordered:
		return ev_port->stats.tx_sched_cnt[DLB2_SCHED_UNORDERED];

	case tx_sched_atomic:
		return ev_port->stats.tx_sched_cnt[DLB2_SCHED_ATOMIC];

	case tx_sched_directed:
		return ev_port->stats.tx_sched_cnt[DLB2_SCHED_DIRECTED];

	case tx_invalid: return ev_port->stats.tx_invalid;

	case outstanding_releases: return ev_port->outstanding_releases;

	case max_outstanding_releases:
		return DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;

	case rx_sched_ordered:
		return ev_port->stats.rx_sched_cnt[DLB2_SCHED_ORDERED];

	case rx_sched_unordered:
		return ev_port->stats.rx_sched_cnt[DLB2_SCHED_UNORDERED];

	case rx_sched_atomic:
		return ev_port->stats.rx_sched_cnt[DLB2_SCHED_ATOMIC];

	case rx_sched_directed:
		return ev_port->stats.rx_sched_cnt[DLB2_SCHED_DIRECTED];

	case rx_sched_invalid: return ev_port->stats.rx_sched_invalid;

	default: return -1;
	}
}

static uint64_t
dlb2_get_threshold_stat(struct dlb2_eventdev *dlb2, int qid, int stat)
{
	int port = 0;
	uint64_t tally = 0;

	for (port = 0; port < DLB2_MAX_NUM_PORTS(dlb2->version); port++)
		tally += dlb2->ev_ports[port].stats.queue[qid].qid_depth[stat];

	return tally;
}

static uint64_t
dlb2_get_enq_ok_stat(struct dlb2_eventdev *dlb2, int qid)
{
	int port = 0;
	uint64_t enq_ok_tally = 0;

	for (port = 0; port < DLB2_MAX_NUM_PORTS(dlb2->version); port++)
		enq_ok_tally += dlb2->ev_ports[port].stats.queue[qid].enq_ok;

	return enq_ok_tally;
}

static uint64_t
get_queue_stat(struct dlb2_eventdev *dlb2, uint16_t obj_idx,
	       enum dlb2_xstats_type type, int extra_arg __rte_unused)
{
	struct dlb2_eventdev_queue *ev_queue =
		&dlb2->ev_queues[obj_idx];

	switch (type) {
	case is_configured: return ev_queue->setup_done;

	case is_load_balanced: return !ev_queue->qm_queue.is_directed;

	case hw_id: return ev_queue->qm_queue.id;

	case num_links: return ev_queue->num_links;

	case sched_type: return ev_queue->qm_queue.sched_type;

	case enq_ok: return dlb2_get_enq_ok_stat(dlb2, obj_idx);

	case current_depth: return dlb2_get_queue_depth(dlb2, ev_queue);

	case depth_threshold: return ev_queue->depth_threshold;

	case depth_le50_threshold:
		return dlb2_get_threshold_stat(dlb2, ev_queue->id,
					       DLB2_QID_DEPTH_LE50);

	case depth_gt50_le75_threshold:
		return dlb2_get_threshold_stat(dlb2, ev_queue->id,
					       DLB2_QID_DEPTH_GT50_LE75);

	case depth_gt75_le100_threshold:
		return dlb2_get_threshold_stat(dlb2, ev_queue->id,
					       DLB2_QID_DEPTH_GT75_LE100);

	case depth_gt100_threshold:
		return dlb2_get_threshold_stat(dlb2, ev_queue->id,
					       DLB2_QID_DEPTH_GT100);

	default: return -1;
	}
}

int
dlb2_xstats_init(struct dlb2_eventdev *dlb2)
{
	/*
	 * define the stats names and types. Used to build up the device
	 * xstats array
	 * There are multiple set of stats:
	 *   - device-level,
	 *   - per-port,
	 *   - per-qid,
	 *
	 * For each of these sets, we have three parallel arrays, one for the
	 * names, the other for the stat type parameter to be passed in the fn
	 * call to get that stat. The third array allows resetting or not.
	 * All these arrays must be kept in sync
	 */
	static const char * const dev_stats[] = {
		"rx_ok",
		"rx_drop",
		"rx_interrupt_wait",
		"rx_umonitor_umwait",
		"tx_ok",
		"total_polls",
		"zero_polls",
		"tx_nospc_ldb_hw_credits",
		"tx_nospc_dir_hw_credits",
		"tx_nospc_hw_credits",
		"tx_nospc_inflight_max",
		"tx_nospc_new_event_limit",
		"tx_nospc_inflight_credits",
		"nb_events_limit",
		"inflight_events",
		"ldb_pool_size",
		"dir_pool_size",
		"pool_size",
	};
	static const enum dlb2_xstats_type dev_types[] = {
		rx_ok,
		rx_drop,
		rx_interrupt_wait,
		rx_umonitor_umwait,
		tx_ok,
		total_polls,
		zero_polls,
		tx_nospc_ldb_hw_credits,
		tx_nospc_dir_hw_credits,
		tx_nospc_hw_credits,
		tx_nospc_inflight_max,
		tx_nospc_new_event_limit,
		tx_nospc_inflight_credits,
		nb_events_limit,
		inflight_events,
		ldb_pool_size,
		dir_pool_size,
		pool_size,
	};
	/* Note: generated device stats are not allowed to be reset. */
	static const uint8_t dev_reset_allowed[] = {
		0, /* rx_ok */
		0, /* rx_drop */
		0, /* rx_interrupt_wait */
		0, /* rx_umonitor_umwait */
		0, /* tx_ok */
		0, /* total_polls */
		0, /* zero_polls */
		0, /* tx_nospc_ldb_hw_credits */
		0, /* tx_nospc_dir_hw_credits */
		0, /* tx_nospc_hw_credits */
		0, /* tx_nospc_inflight_max */
		0, /* tx_nospc_new_event_limit */
		0, /* tx_nospc_inflight_credits */
		0, /* nb_events_limit */
		0, /* inflight_events */
		0, /* ldb_pool_size */
		0, /* dir_pool_size */
		0, /* pool_size */
	};
	static const char * const port_stats[] = {
		"is_configured",
		"is_load_balanced",
		"hw_id",
		"rx_ok",
		"rx_drop",
		"rx_interrupt_wait",
		"rx_umonitor_umwait",
		"tx_ok",
		"total_polls",
		"zero_polls",
		"tx_nospc_ldb_hw_credits",
		"tx_nospc_dir_hw_credits",
		"tx_nospc_hw_credits",
		"tx_nospc_inflight_max",
		"tx_nospc_new_event_limit",
		"tx_nospc_inflight_credits",
		"tx_new",
		"tx_fwd",
		"tx_rel",
		"tx_implicit_rel",
		"tx_sched_ordered",
		"tx_sched_unordered",
		"tx_sched_atomic",
		"tx_sched_directed",
		"tx_invalid",
		"outstanding_releases",
		"max_outstanding_releases",
		"rx_sched_ordered",
		"rx_sched_unordered",
		"rx_sched_atomic",
		"rx_sched_directed",
		"rx_sched_invalid"
	};
	static const enum dlb2_xstats_type port_types[] = {
		is_configured,
		is_load_balanced,
		hw_id,
		rx_ok,
		rx_drop,
		rx_interrupt_wait,
		rx_umonitor_umwait,
		tx_ok,
		total_polls,
		zero_polls,
		tx_nospc_ldb_hw_credits,
		tx_nospc_dir_hw_credits,
		tx_nospc_hw_credits,
		tx_nospc_inflight_max,
		tx_nospc_new_event_limit,
		tx_nospc_inflight_credits,
		tx_new,
		tx_fwd,
		tx_rel,
		tx_implicit_rel,
		tx_sched_ordered,
		tx_sched_unordered,
		tx_sched_atomic,
		tx_sched_directed,
		tx_invalid,
		outstanding_releases,
		max_outstanding_releases,
		rx_sched_ordered,
		rx_sched_unordered,
		rx_sched_atomic,
		rx_sched_directed,
		rx_sched_invalid
	};
	static const uint8_t port_reset_allowed[] = {
		0, /* is_configured */
		0, /* is_load_balanced */
		0, /* hw_id */
		1, /* rx_ok */
		1, /* rx_drop */
		1, /* rx_interrupt_wait */
		1, /* rx_umonitor_umwait */
		1, /* tx_ok */
		1, /* total_polls */
		1, /* zero_polls */
		1, /* tx_nospc_ldb_hw_credits */
		1, /* tx_nospc_dir_hw_credits */
		1, /* tx_nospc_hw_credits */
		1, /* tx_nospc_inflight_max */
		1, /* tx_nospc_new_event_limit */
		1, /* tx_nospc_inflight_credits */
		1, /* tx_new */
		1, /* tx_fwd */
		1, /* tx_rel */
		1, /* tx_implicit_rel */
		1, /* tx_sched_ordered */
		1, /* tx_sched_unordered */
		1, /* tx_sched_atomic */
		1, /* tx_sched_directed */
		1, /* tx_invalid */
		0, /* outstanding_releases */
		0, /* max_outstanding_releases */
		1, /* rx_sched_ordered */
		1, /* rx_sched_unordered */
		1, /* rx_sched_atomic */
		1, /* rx_sched_directed */
		1  /* rx_sched_invalid */
	};

	/* QID specific stats */
	static const char * const qid_stats[] = {
		"is_configured",
		"is_load_balanced",
		"hw_id",
		"num_links",
		"sched_type",
		"enq_ok",
		"current_depth",
		"depth_threshold",
		"depth_le50_threshold",
		"depth_gt50_le75_threshold",
		"depth_gt75_le100_threshold",
		"depth_gt100_threshold",
	};
	static const enum dlb2_xstats_type qid_types[] = {
		is_configured,
		is_load_balanced,
		hw_id,
		num_links,
		sched_type,
		enq_ok,
		current_depth,
		depth_threshold,
		depth_le50_threshold,
		depth_gt50_le75_threshold,
		depth_gt75_le100_threshold,
		depth_gt100_threshold,
	};
	static const uint8_t qid_reset_allowed[] = {
		0, /* is_configured */
		0, /* is_load_balanced */
		0, /* hw_id */
		0, /* num_links */
		0, /* sched_type */
		1, /* enq_ok */
		0, /* current_depth */
		0, /* depth_threshold */
		1, /* depth_le50_threshold */
		1, /* depth_gt50_le75_threshold */
		1, /* depth_gt75_le100_threshold */
		1, /* depth_gt100_threshold */
	};

	/* ---- end of stat definitions ---- */

	/* check sizes, since a missed comma can lead to strings being
	 * joined by the compiler.
	 */
	RTE_BUILD_BUG_ON(RTE_DIM(dev_stats) != RTE_DIM(dev_types));
	RTE_BUILD_BUG_ON(RTE_DIM(port_stats) != RTE_DIM(port_types));
	RTE_BUILD_BUG_ON(RTE_DIM(qid_stats) != RTE_DIM(qid_types));

	RTE_BUILD_BUG_ON(RTE_DIM(dev_stats) != RTE_DIM(dev_reset_allowed));
	RTE_BUILD_BUG_ON(RTE_DIM(port_stats) != RTE_DIM(port_reset_allowed));
	RTE_BUILD_BUG_ON(RTE_DIM(qid_stats) != RTE_DIM(qid_reset_allowed));

	/* other vars */
	const unsigned int count = RTE_DIM(dev_stats) +
		DLB2_MAX_NUM_PORTS(dlb2->version) * RTE_DIM(port_stats) +
		DLB2_MAX_NUM_QUEUES(dlb2->version) * RTE_DIM(qid_stats);
	unsigned int i, port, qid, stat_id = 0;

	dlb2->xstats = rte_zmalloc_socket(NULL,
			sizeof(dlb2->xstats[0]) * count, 0,
			dlb2->qm_instance.info.socket_id);
	if (dlb2->xstats == NULL)
		return -ENOMEM;

#define sname dlb2->xstats[stat_id].name.name
	for (i = 0; i < RTE_DIM(dev_stats); i++, stat_id++) {
		dlb2->xstats[stat_id] = (struct dlb2_xstats_entry) {
			.fn_id = DLB2_XSTATS_FN_DEV,
			.stat = dev_types[i],
			.mode = RTE_EVENT_DEV_XSTATS_DEVICE,
			.reset_allowed = dev_reset_allowed[i],
		};
		snprintf(sname, sizeof(sname), "dev_%s", dev_stats[i]);
	}
	dlb2->xstats_count_mode_dev = stat_id;

	for (port = 0; port < DLB2_MAX_NUM_PORTS(dlb2->version); port++) {
		dlb2->xstats_offset_for_port[port] = stat_id;

		uint32_t count_offset = stat_id;

		for (i = 0; i < RTE_DIM(port_stats); i++, stat_id++) {
			dlb2->xstats[stat_id] = (struct dlb2_xstats_entry){
				.fn_id = DLB2_XSTATS_FN_PORT,
				.obj_idx = port,
				.stat = port_types[i],
				.mode = RTE_EVENT_DEV_XSTATS_PORT,
				.reset_allowed = port_reset_allowed[i],
			};
			snprintf(sname, sizeof(sname), "port_%u_%s",
				 port, port_stats[i]);
		}

		dlb2->xstats_count_per_port[port] = stat_id - count_offset;
	}

	dlb2->xstats_count_mode_port = stat_id - dlb2->xstats_count_mode_dev;

	for (qid = 0; qid < DLB2_MAX_NUM_QUEUES(dlb2->version); qid++) {
		uint32_t count_offset = stat_id;

		dlb2->xstats_offset_for_qid[qid] = stat_id;

		for (i = 0; i < RTE_DIM(qid_stats); i++, stat_id++) {
			dlb2->xstats[stat_id] = (struct dlb2_xstats_entry){
				.fn_id = DLB2_XSTATS_FN_QUEUE,
				.obj_idx = qid,
				.stat = qid_types[i],
				.mode = RTE_EVENT_DEV_XSTATS_QUEUE,
				.reset_allowed = qid_reset_allowed[i],
			};
			snprintf(sname, sizeof(sname), "qid_%u_%s",
				 qid, qid_stats[i]);
		}

		dlb2->xstats_count_per_qid[qid] = stat_id - count_offset;
	}

	dlb2->xstats_count_mode_queue = stat_id -
		(dlb2->xstats_count_mode_dev + dlb2->xstats_count_mode_port);
#undef sname

	dlb2->xstats_count = stat_id;

	return 0;
}

void
dlb2_xstats_uninit(struct dlb2_eventdev *dlb2)
{
	rte_free(dlb2->xstats);
	dlb2->xstats_count = 0;
}

int
dlb2_eventdev_xstats_get_names(const struct rte_eventdev *dev,
		enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,
		struct rte_event_dev_xstats_name *xstats_names,
		unsigned int *ids, unsigned int size)
{
	const struct dlb2_eventdev *dlb2 = dlb2_pmd_priv(dev);
	unsigned int i;
	unsigned int xidx = 0;
	uint32_t xstats_mode_count = 0;
	uint32_t start_offset = 0;

	switch (mode) {
	case RTE_EVENT_DEV_XSTATS_DEVICE:
		xstats_mode_count = dlb2->xstats_count_mode_dev;
		break;
	case RTE_EVENT_DEV_XSTATS_PORT:
		if (queue_port_id >= DLB2_MAX_NUM_PORTS(dlb2->version))
			break;
		xstats_mode_count = dlb2->xstats_count_per_port[queue_port_id];
		start_offset = dlb2->xstats_offset_for_port[queue_port_id];
		break;
	case RTE_EVENT_DEV_XSTATS_QUEUE:
		if (queue_port_id >= DLB2_MAX_NUM_QUEUES(dlb2->version) &&
		    (DLB2_MAX_NUM_QUEUES(dlb2->version) <= 255))
			break;
		xstats_mode_count = dlb2->xstats_count_per_qid[queue_port_id];
		start_offset = dlb2->xstats_offset_for_qid[queue_port_id];
		break;
	default:
		return -EINVAL;
	};

	if (xstats_mode_count > size || ids == NULL || xstats_names == NULL)
		return xstats_mode_count;

	for (i = 0; i < dlb2->xstats_count && xidx < size; i++) {
		if (dlb2->xstats[i].mode != mode)
			continue;

		if (mode != RTE_EVENT_DEV_XSTATS_DEVICE &&
		    queue_port_id != dlb2->xstats[i].obj_idx)
			continue;

		xstats_names[xidx] = dlb2->xstats[i].name;
		if (ids)
			ids[xidx] = start_offset + xidx;
		xidx++;
	}
	return xidx;
}

static int
dlb2_xstats_update(struct dlb2_eventdev *dlb2,
		enum rte_event_dev_xstats_mode mode,
		uint8_t queue_port_id, const unsigned int ids[],
		uint64_t values[], unsigned int n, const uint32_t reset)
{
	unsigned int i;
	unsigned int xidx = 0;
	uint32_t xstats_mode_count = 0;

	switch (mode) {
	case RTE_EVENT_DEV_XSTATS_DEVICE:
		xstats_mode_count = dlb2->xstats_count_mode_dev;
		break;
	case RTE_EVENT_DEV_XSTATS_PORT:
		if (queue_port_id >= DLB2_MAX_NUM_PORTS(dlb2->version))
			goto invalid_value;
		xstats_mode_count = dlb2->xstats_count_per_port[queue_port_id];
		break;
	case RTE_EVENT_DEV_XSTATS_QUEUE:
#if (DLB2_MAX_NUM_QUEUES(DLB2_HW_V2_5) <= 255) /* max 8 bit value */
		if (queue_port_id >= DLB2_MAX_NUM_QUEUES(dlb2->version))
			goto invalid_value;
#endif
		xstats_mode_count = dlb2->xstats_count_per_qid[queue_port_id];
		break;
	default:
		goto invalid_value;
	};

	for (i = 0; i < n && xidx < xstats_mode_count; i++) {
		struct dlb2_xstats_entry *xs = &dlb2->xstats[ids[i]];
		dlb2_xstats_fn fn;

		if (ids[i] > dlb2->xstats_count || xs->mode != mode)
			continue;

		if (mode != RTE_EVENT_DEV_XSTATS_DEVICE &&
		    queue_port_id != xs->obj_idx)
			continue;

		switch (xs->fn_id) {
		case DLB2_XSTATS_FN_DEV:
			fn = get_dev_stat;
			break;
		case DLB2_XSTATS_FN_PORT:
			fn = get_port_stat;
			break;
		case DLB2_XSTATS_FN_QUEUE:
			fn = get_queue_stat;
			break;
		default:
			DLB2_LOG_ERR("Unexpected xstat fn_id %d\n", xs->fn_id);
			goto invalid_value;
		}

		uint64_t val = fn(dlb2, xs->obj_idx, xs->stat,
				  xs->extra_arg) - xs->reset_value;

		if (values)
			values[xidx] = val;

		if (xs->reset_allowed && reset)
			xs->reset_value += val;

		xidx++;
	}

	return xidx;

invalid_value:
	return -EINVAL;
}

int
dlb2_eventdev_xstats_get(const struct rte_eventdev *dev,
		enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,
		const unsigned int ids[], uint64_t values[], unsigned int n)
{
	struct dlb2_eventdev *dlb2 = dlb2_pmd_priv(dev);
	const uint32_t reset = 0;

	return dlb2_xstats_update(dlb2, mode, queue_port_id, ids, values, n,
				  reset);
}

uint64_t
dlb2_eventdev_xstats_get_by_name(const struct rte_eventdev *dev,
				 const char *name, unsigned int *id)
{
	struct dlb2_eventdev *dlb2 = dlb2_pmd_priv(dev);
	unsigned int i;
	dlb2_xstats_fn fn;

	for (i = 0; i < dlb2->xstats_count; i++) {
		struct dlb2_xstats_entry *xs = &dlb2->xstats[i];

		if (strncmp(xs->name.name, name,
			    RTE_EVENT_DEV_XSTATS_NAME_SIZE) == 0){
			if (id != NULL)
				*id = i;

			switch (xs->fn_id) {
			case DLB2_XSTATS_FN_DEV:
				fn = get_dev_stat;
				break;
			case DLB2_XSTATS_FN_PORT:
				fn = get_port_stat;
				break;
			case DLB2_XSTATS_FN_QUEUE:
				fn = get_queue_stat;
				break;
			default:
				DLB2_LOG_ERR("Unexpected xstat fn_id %d\n",
					  xs->fn_id);
				return (uint64_t)-1;
			}

			return fn(dlb2, xs->obj_idx, xs->stat,
				  xs->extra_arg) - xs->reset_value;
		}
	}
	if (id != NULL)
		*id = (uint32_t)-1;
	return (uint64_t)-1;
}

static void
dlb2_xstats_reset_range(struct dlb2_eventdev *dlb2, uint32_t start,
			uint32_t num)
{
	uint32_t i;
	dlb2_xstats_fn fn;

	for (i = start; i < start + num; i++) {
		struct dlb2_xstats_entry *xs = &dlb2->xstats[i];

		if (!xs->reset_allowed)
			continue;

		switch (xs->fn_id) {
		case DLB2_XSTATS_FN_DEV:
			fn = get_dev_stat;
			break;
		case DLB2_XSTATS_FN_PORT:
			fn = get_port_stat;
			break;
		case DLB2_XSTATS_FN_QUEUE:
			fn = get_queue_stat;
			break;
		default:
			DLB2_LOG_ERR("Unexpected xstat fn_id %d\n", xs->fn_id);
			return;
		}

		uint64_t val = fn(dlb2, xs->obj_idx, xs->stat, xs->extra_arg);
		xs->reset_value = val;
	}
}

static int
dlb2_xstats_reset_queue(struct dlb2_eventdev *dlb2, uint8_t queue_id,
			const uint32_t ids[], uint32_t nb_ids)
{
	const uint32_t reset = 1;

	if (ids) {
		uint32_t nb_reset = dlb2_xstats_update(dlb2,
					RTE_EVENT_DEV_XSTATS_QUEUE,
					queue_id, ids, NULL, nb_ids,
					reset);
		return nb_reset == nb_ids ? 0 : -EINVAL;
	}

	if (ids == NULL)
		dlb2_xstats_reset_range(dlb2,
			dlb2->xstats_offset_for_qid[queue_id],
			dlb2->xstats_count_per_qid[queue_id]);

	return 0;
}

static int
dlb2_xstats_reset_port(struct dlb2_eventdev *dlb2, uint8_t port_id,
		       const uint32_t ids[], uint32_t nb_ids)
{
	const uint32_t reset = 1;
	int offset = dlb2->xstats_offset_for_port[port_id];
	int nb_stat = dlb2->xstats_count_per_port[port_id];

	if (ids) {
		uint32_t nb_reset = dlb2_xstats_update(dlb2,
					RTE_EVENT_DEV_XSTATS_PORT, port_id,
					ids, NULL, nb_ids,
					reset);
		return nb_reset == nb_ids ? 0 : -EINVAL;
	}

	dlb2_xstats_reset_range(dlb2, offset, nb_stat);
	return 0;
}

static int
dlb2_xstats_reset_dev(struct dlb2_eventdev *dlb2, const uint32_t ids[],
		      uint32_t nb_ids)
{
	uint32_t i;

	if (ids) {
		for (i = 0; i < nb_ids; i++) {
			uint32_t id = ids[i];

			if (id >= dlb2->xstats_count_mode_dev)
				return -EINVAL;
			dlb2_xstats_reset_range(dlb2, id, 1);
		}
	} else {
		for (i = 0; i < dlb2->xstats_count_mode_dev; i++)
			dlb2_xstats_reset_range(dlb2, i, 1);
	}

	return 0;
}

int
dlb2_eventdev_xstats_reset(struct rte_eventdev *dev,
			   enum rte_event_dev_xstats_mode mode,
			   int16_t queue_port_id,
			   const uint32_t ids[],
			   uint32_t nb_ids)
{
	struct dlb2_eventdev *dlb2 = dlb2_pmd_priv(dev);
	uint32_t i;

	/* handle -1 for queue_port_id here, looping over all ports/queues */
	switch (mode) {
	case RTE_EVENT_DEV_XSTATS_DEVICE:
		if (dlb2_xstats_reset_dev(dlb2, ids, nb_ids))
			return -EINVAL;
		break;
	case RTE_EVENT_DEV_XSTATS_PORT:
		if (queue_port_id == -1) {
			for (i = 0;
			     i < DLB2_MAX_NUM_PORTS(dlb2->version); i++) {
				if (dlb2_xstats_reset_port(dlb2, i,
							   ids, nb_ids))
					return -EINVAL;
			}
		} else if (queue_port_id < DLB2_MAX_NUM_PORTS(dlb2->version)) {
			if (dlb2_xstats_reset_port(dlb2, queue_port_id,
						   ids, nb_ids))
				return -EINVAL;
		}
		break;
	case RTE_EVENT_DEV_XSTATS_QUEUE:
		if (queue_port_id == -1) {
			for (i = 0;
			     i < DLB2_MAX_NUM_QUEUES(dlb2->version); i++) {
				if (dlb2_xstats_reset_queue(dlb2, i,
							    ids, nb_ids))
					return -EINVAL;
			}
		} else if (queue_port_id < DLB2_MAX_NUM_QUEUES(dlb2->version)) {
			if (dlb2_xstats_reset_queue(dlb2, queue_port_id,
						    ids, nb_ids))
				return -EINVAL;
		}
		break;
	};

	return 0;
}

void
dlb2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
{
	struct dlb2_eventdev *dlb2;
	struct dlb2_hw_dev *handle;
	int i;

	dlb2 = dlb2_pmd_priv(dev);

	if (dlb2 == NULL) {
		fprintf(f, "DLB2 Event device cannot be dumped!\n");
		return;
	}

	if (!dlb2->configured)
		fprintf(f, "DLB2 Event device is not configured\n");

	handle = &dlb2->qm_instance;

	fprintf(f, "================\n");
	fprintf(f, "DLB2 Device Dump\n");
	fprintf(f, "================\n");

	fprintf(f, "Processor supports umonitor/umwait instructions = %s\n",
		dlb2->umwait_allowed ? "yes" : "no");

	/* Generic top level device information */

	fprintf(f, "device is configured and run state =");
	if (dlb2->run_state == DLB2_RUN_STATE_STOPPED)
		fprintf(f, "STOPPED\n");
	else if (dlb2->run_state == DLB2_RUN_STATE_STOPPING)
		fprintf(f, "STOPPING\n");
	else if (dlb2->run_state == DLB2_RUN_STATE_STARTING)
		fprintf(f, "STARTING\n");
	else if (dlb2->run_state == DLB2_RUN_STATE_STARTED)
		fprintf(f, "STARTED\n");
	else
		fprintf(f, "UNEXPECTED\n");

	fprintf(f, "domain ID=%u, socket_id=%u, evdev=%p\n",
		handle->domain_id, handle->info.socket_id, dlb2->event_dev);

	fprintf(f, "num dir ports=%u, num dir queues=%u\n",
		dlb2->num_dir_ports, dlb2->num_dir_queues);

	fprintf(f, "num ldb ports=%u, num ldb queues=%u\n",
		dlb2->num_ldb_ports, dlb2->num_ldb_queues);

	fprintf(f, "num atomic inflights=%u, hist list entries=%u\n",
		handle->cfg.resources.num_atomic_inflights,
		handle->cfg.resources.num_hist_list_entries);

	fprintf(f, "results from most recent hw resource query:\n");

	fprintf(f, "\tnum_sched_domains = %u\n",
		dlb2->hw_rsrc_query_results.num_sched_domains);

	fprintf(f, "\tnum_ldb_queues = %u\n",
		dlb2->hw_rsrc_query_results.num_ldb_queues);

	fprintf(f, "\tnum_ldb_ports = %u\n",
		dlb2->hw_rsrc_query_results.num_ldb_ports);

	fprintf(f, "\tnum_dir_ports = %u\n",
		dlb2->hw_rsrc_query_results.num_dir_ports);

	fprintf(f, "\tnum_atomic_inflights = %u\n",
		dlb2->hw_rsrc_query_results.num_atomic_inflights);

	fprintf(f, "\tnum_hist_list_entries = %u\n",
		dlb2->hw_rsrc_query_results.num_hist_list_entries);

	fprintf(f, "\tmax_contiguous_hist_list_entries = %u\n",
		dlb2->hw_rsrc_query_results.max_contiguous_hist_list_entries);

	fprintf(f, "\tnum_ldb_credits = %u\n",
		dlb2->hw_rsrc_query_results.num_ldb_credits);

	fprintf(f, "\tnum_dir_credits = %u\n",
		dlb2->hw_rsrc_query_results.num_dir_credits);

	fprintf(f, "\tnum_credits = %u\n",
		dlb2->hw_rsrc_query_results.num_credits);

	/* Port level information */

	for (i = 0; i < dlb2->num_ports; i++) {
		struct dlb2_eventdev_port *p = &dlb2->ev_ports[i];
		int j;

		if (!p->enq_configured)
			fprintf(f, "Port_%d is not configured\n", i);

		fprintf(f, "Port_%d\n", i);
		fprintf(f, "=======\n");

		fprintf(f, "\tevport_%u is configured, setup done=%d\n",
			p->id, p->setup_done);

		fprintf(f, "\tconfig state=%d, port state=%d\n",
			p->qm_port.config_state, p->qm_port.state);

		fprintf(f, "\tport is %s\n",
			p->qm_port.is_directed ? "directed" : "load balanced");

		fprintf(f, "\toutstanding releases=%u\n",
			p->outstanding_releases);

		fprintf(f, "\tinflight max=%u, inflight credits=%u\n",
			p->inflight_max, p->inflight_credits);

		fprintf(f, "\tcredit update quanta=%u, implicit release =%u\n",
			p->credit_update_quanta, p->implicit_release);

		fprintf(f, "\tnum_links=%d, queues -> ", p->num_links);

		for (j = 0; j < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; j++) {
			if (p->link[j].valid)
				fprintf(f, "id=%u prio=%u ",
					p->link[j].queue_id,
					p->link[j].priority);
		}
		fprintf(f, "\n");

		fprintf(f, "\thardware port id=%u\n", p->qm_port.id);

		fprintf(f, "\tcached_ldb_credits=%u\n",
			p->qm_port.cached_ldb_credits);

		fprintf(f, "\tldb_credits = %u\n",
			p->qm_port.ldb_credits);

		fprintf(f, "\tcached_dir_credits = %u\n",
			p->qm_port.cached_dir_credits);

		fprintf(f, "\tdir_credits = %u\n",
			p->qm_port.dir_credits);

		fprintf(f, "\tcached_credits = %u\n",
			p->qm_port.cached_credits);

		fprintf(f, "\tdir_credits = %u\n",
			p->qm_port.credits);

		fprintf(f, "\tgenbit=%d, cq_idx=%d, cq_depth=%d\n",
			p->qm_port.gen_bit,
			p->qm_port.cq_idx,
			p->qm_port.cq_depth);

		fprintf(f, "\tinterrupt armed=%d\n",
			p->qm_port.int_armed);

		fprintf(f, "\tPort statistics\n");

		fprintf(f, "\t\trx_ok %" PRIu64 "\n",
			p->stats.traffic.rx_ok);

		fprintf(f, "\t\trx_drop %" PRIu64 "\n",
			p->stats.traffic.rx_drop);

		fprintf(f, "\t\trx_interrupt_wait %" PRIu64 "\n",
			p->stats.traffic.rx_interrupt_wait);

		fprintf(f, "\t\trx_umonitor_umwait %" PRIu64 "\n",
			p->stats.traffic.rx_umonitor_umwait);

		fprintf(f, "\t\ttx_ok %" PRIu64 "\n",
			p->stats.traffic.tx_ok);

		fprintf(f, "\t\ttotal_polls %" PRIu64 "\n",
			p->stats.traffic.total_polls);

		fprintf(f, "\t\tzero_polls %" PRIu64 "\n",
			p->stats.traffic.zero_polls);

		fprintf(f, "\t\ttx_nospc_ldb_hw_credits %" PRIu64 "\n",
			p->stats.traffic.tx_nospc_ldb_hw_credits);

		fprintf(f, "\t\ttx_nospc_dir_hw_credits %" PRIu64 "\n",
			p->stats.traffic.tx_nospc_dir_hw_credits);

		fprintf(f, "\t\ttx_nospc_hw_credits %" PRIu64 "\n",
			p->stats.traffic.tx_nospc_hw_credits);

		fprintf(f, "\t\ttx_nospc_inflight_max %" PRIu64 "\n",
			p->stats.traffic.tx_nospc_inflight_max);

		fprintf(f, "\t\ttx_nospc_new_event_limit %" PRIu64 "\n",
			p->stats.traffic.tx_nospc_new_event_limit);

		fprintf(f, "\t\ttx_nospc_inflight_credits %" PRIu64 "\n",
			p->stats.traffic.tx_nospc_inflight_credits);

		fprintf(f, "\t\ttx_new %" PRIu64 "\n",
			p->stats.tx_op_cnt[RTE_EVENT_OP_NEW]);

		fprintf(f, "\t\ttx_fwd %" PRIu64 "\n",
			p->stats.tx_op_cnt[RTE_EVENT_OP_FORWARD]);

		fprintf(f, "\t\ttx_rel %" PRIu64 "\n",
			p->stats.tx_op_cnt[RTE_EVENT_OP_RELEASE]);

		fprintf(f, "\t\ttx_implicit_rel %" PRIu64 "\n",
			p->stats.tx_implicit_rel);

		fprintf(f, "\t\ttx_sched_ordered %" PRIu64 "\n",
			p->stats.tx_sched_cnt[DLB2_SCHED_ORDERED]);

		fprintf(f, "\t\ttx_sched_unordered %" PRIu64 "\n",
			p->stats.tx_sched_cnt[DLB2_SCHED_UNORDERED]);

		fprintf(f, "\t\ttx_sched_atomic %" PRIu64 "\n",
			p->stats.tx_sched_cnt[DLB2_SCHED_ATOMIC]);

		fprintf(f, "\t\ttx_sched_directed %" PRIu64 "\n",
			p->stats.tx_sched_cnt[DLB2_SCHED_DIRECTED]);

		fprintf(f, "\t\ttx_invalid %" PRIu64 "\n",
			p->stats.tx_invalid);

		fprintf(f, "\t\trx_sched_ordered %" PRIu64 "\n",
			p->stats.rx_sched_cnt[DLB2_SCHED_ORDERED]);

		fprintf(f, "\t\trx_sched_unordered %" PRIu64 "\n",
			p->stats.rx_sched_cnt[DLB2_SCHED_UNORDERED]);

		fprintf(f, "\t\trx_sched_atomic %" PRIu64 "\n",
			p->stats.rx_sched_cnt[DLB2_SCHED_ATOMIC]);

		fprintf(f, "\t\trx_sched_directed %" PRIu64 "\n",
			p->stats.rx_sched_cnt[DLB2_SCHED_DIRECTED]);

		fprintf(f, "\t\trx_sched_invalid %" PRIu64 "\n",
			p->stats.rx_sched_invalid);
	}

	/* Queue level information */

	for (i = 0; i < dlb2->num_queues; i++) {
		struct dlb2_eventdev_queue *q = &dlb2->ev_queues[i];
		int j, k;

		if (!q->setup_done)
			fprintf(f, "Queue_%d is not configured\n", i);

		fprintf(f, "Queue_%d\n", i);
		fprintf(f, "========\n");

		fprintf(f, "\tevqueue_%u is set up\n", q->id);

		fprintf(f, "\tqueue is %s\n",
			q->qm_queue.is_directed ? "directed" : "load balanced");

		fprintf(f, "\tnum_links=%d, ports -> ", q->num_links);

		for (j = 0; j < dlb2->num_ports; j++) {
			struct dlb2_eventdev_port *p = &dlb2->ev_ports[j];

			for (k = 0; k < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; k++) {
				if (p->link[k].valid &&
				    p->link[k].queue_id == q->id)
					fprintf(f, "id=%u prio=%u ",
						p->id, p->link[k].priority);
			}
		}
		fprintf(f, "\n");

		fprintf(f, "\tcurrent depth: %u events\n",
			dlb2_get_queue_depth(dlb2, q));

		fprintf(f, "\tnum qid inflights=%u, sched_type=%d\n",
			q->qm_queue.num_qid_inflights, q->qm_queue.sched_type);
	}
}